As integrated circuit technology continues to scale down, energy efficiency becomes increasingly important. To that end, group III-V semiconductor materials have been proposed for use in future generation transistors because of their ability to enable high-speed switching at low supply voltages due to their excellent low and high-field electron transport properties. Group III-V materials are synthesized using elements from the 3rd and the 5th group of the periodic table, examples include gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium nitride (GaN), gallium aluminum arsenide (GaAlAs), indium aluminum arsenide (InAlAs), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb).
Transistors developed using III-V materials are known as quantum-well field-effect transistors (QWFETs). In a QWFET, the III-V material is used to form a quantum-well channel region for the transistor while the source and drain (S/D) regions are formed using a metal-doped semiconducting material, such as doped silicon or doped germanium. Conventional lithography processes are used to form the gate stack and source/drain regions for the QWFET device. This results in a relatively large distance between the gate electrode and the source/drain regions.
While self-aligned techniques can minimize the distance between the S/D regions and the gate stack, unfortunately, they cannot be used in the fabrication of QWFET devices. This is because conventional self-aligned techniques rely heavily on the use of spacers to define where structures are to be formed. In the fabrication of QWFET devices, however, the spacer material is difficult to form and suffers greatly from etch damage during dry etch steps. As a result, alternate processes are needed to form self-aligned QWFET devices that minimize the distance between the S/D regions and the gate electrode.